The size, shape, and quality of the polysilicon gate of MOSFETs are of particular concern for conventional as well as future scaled-down MOSFETs.
In order to be able to make memory chips and logic devices of higher integration density than currently feasible, one has to find a way to further scale down the gates used in such chips and devices and to improve the accuracy at which such gates are made.
The basic elements of a conventional MOSFET 10 are schematically illustrated in FIG. 1. Such an FET 10 typically is formed in a silicon substrate 11 and comprises a doped source region 14 and a doped drain region 12 being arranged to the left and right of a polysilicon gate pillar 13. This gate pillar 13 is separated from the channel 17--which is situated between the source 14 and drain regions 12--by an oxide layer 15. Underneath the polysilicon gate 13, the oxide layer 15 serves as gate oxide. In conventional FETs, the gate oxide is thicker underneath the polysilicon gate, because the portions of the oxide layer 15 not covered by the polysilicon gate are attacked during the polysilicon RIE, as addressed in the following. Please note that the source/channel and drain/channel junctions 18 are not abruptly defined. The dopant concentration decreases the closer one gets to the actual channel, i.e. the source/channel and drain/channel junctions 18 are not well defined. This is mainly caused by the sloped side walls 16 of the gate 13 which permit dopants to reach the silicon substrate near the gate edges (overlapping the gate) when the source and drain regions 12 and 14 are implanted from the top. This results in increased source and drain resistance, high overlap capacitance, and ill defined effective channel length resulting in degrading the device performance.
In the present state of the art, silicon reactive ion etching (RIE) and a photo-resist mask are used to define the polysilicon gates of MOSFETs, including complementary metal oxide semiconductor (CMOS) FETs. Two requirements have to be satisfied by the RIE process. The polysilicon gates should have perfectly vertical side walls, and furthermore, one has to ensure that the RIE process stops on the gate oxide 15 at the bottom of the polysilicon gate 13 without destroying it. Typically, the gate oxide 15 is very thin (in the range of a few nanometers) and becomes thinner and thinner when further scaling down FETs.
When processing whole wafers, the thickness of the polysilicon layer--which is to be etched to become the polysilicon gate of all MOSFETs on the wafer--varies. To ensure that all polysilicon gates are defined properly, one has to adjust the etch time such that all polysilicon gates, including those formed in a section of the wafer where the polysilicon layer is relatively thick, are etched down to the thin gate oxide 15. This intentional over-etching, however, leads to a locally reduced thickness of the gate oxide 15 adjacent to the polysilicon gate 13 (as schematically illustrated in FIG. 1), because the selectivity of the polysilicon etch process is not high enough (please note that high selectivity means that an etch process attacks only the materials it is intended to etch, e.g. the polysilicon in the present example, but not the gate oxide). That is conventional polysilicon RIE etch processes not only attack the polysilicon, but also the oxide layer 15. Due to the low selectivity, the oxide layer 15 is thinner adjacent to the polysilicon gate 13 than the original thickness of the oxide layer (see underneath the polysilicon gate 13), as schematically illustrated in FIG. 1.
It is the nature of the currently used RIE polysilicon etch processes that an improved selectivity reduces the directionality of the etch resulting in undesirable non-vertical (sloped) polysilicon gate side walls 16. In other words, when employing conventional polysilicon RIE processes for the formation of polysilicon gates, either the slope of the side walls increases, or the thin oxide layer 15 is attacked and consequently varies in thickness across the wafer. The polysilicon RIE chemistry can be adjusted to improve the polysilicon/oxide selectivity, but then the RIE etch becomes more isotropic resulting in even more sloped side walls.
As mentioned above, the gate oxide has to become thinner when scaling down the MOSFETs. It is immediately obvious that the thinner the gate oxide is, the less over-etching is acceptable. In other words, the etch selectivity has to be improved in order to be able to make polysilicon gates of very small size. The gate oxide of sub-0.1 micron CMOS FETs, for example, is less than 3 nm thick. Any over-etching impairs the device performance.
The gate length L.sub.G of conventional transistors is defined by photo lithography and a subsequent RIE step, as briefly discussed above. Since the resolution of photo lithography is proportional to the wavelength of the exposing light, the gate length is limited to about 150 nm. Smaller gates can not be made using conventional optical lithography.
Cutting edge production today creates features that are 250 nm wide using 248 nm illumination. Currently, the implementing schemes based on light are the bottleneck when trying to obtain structures of a feature size below 150 nm. State-of-the-art optical lithography systems for making current DRAMs, for example, are quite expensive. The semiconductor industry road map calls for leading-edge manufacturing at 180 nm in the year 2001 and 70 nm in the year 2011.
Alternative processes, such as x-ray lithography, become attractive when moving on to smaller feature sizes, but the required investments are huge. Thus techniques that maintain compatibility with much of the existing processes are inherently valuable.
There are currently no MOSFET fabrication schemes known that would allow to realize MOSFETs with gates of sub-lithographic length and vertical (non-sloped) side walls. Furthermore, the conventional techniques are not suited to make scaled-down FETs having gate lengths of 150 nm and below, as well as intact gate oxides with a thickness of less than 5 nm.
There is some background art of general interest which is related to certain aspects of the invention, such as for example U.S. Pat. No. 4,758,528, U.S. Pat. No. 4,430,791, and U.S. Pat. No. 4,636,822, all three patents currently being assigned to the assignee of the present patent application.
The present patent application is related to U.S. patent application Ser. No. 08/ . . . (Applicant's reference number FI 9-97-165), entitled "FIELD EFFECT TRANSISTORS WITH IMPROVED IMPLANTS AND METHOD FOR MAKING SUCH TRANSISTORS", and U.S. patent application Ser. No. 08/ . . . (Applicant's reference number FI 9-97-164), entitled "FIELD EFFECT TRANSISTORS WITH VERTICAL GATE SIDE WALLS AND METHOD FOR MAKING SUCH TRANSISTORS", both filed on the same day and presently assigned to the assignee of the instant application. The disclosure of these two patent applications is incorporated herein by reference.
It is an object of the present invention to provide a method for the formation of MOSFETs with well defined channel length of less than 150 nm.
It is another object of the present invention to provide a method for the formation of MOSFETs with minimum source and drain resistance, and minimum overlap capacitance.